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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>High-level driver functions are defined in <a class="el" href="xvphy_8h.html" title="The Xilinx Video PHY (VPHY) driver. ">xvphy.h</a>.</p>
<dl class="section note"><dt>Note</dt><dd>None.</dd></dl>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
----- ---- -------- -----------------------------------------------
1.0   als  10/19/15 Initial release.
</pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a4efa6fb68e702bd91a3fb099d7ba0188"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xvphy__hw_8h.html#a4efa6fb68e702bd91a3fb099d7ba0188">XVphy_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;XVphy_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="separator:a4efa6fb68e702bd91a3fb099d7ba0188"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a03d7c5c126a6c25d1ed193dfaa7f4a2c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xvphy__hw_8h.html#a03d7c5c126a6c25d1ed193dfaa7f4a2c">XVphy_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;XVphy_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
<tr class="separator:a03d7c5c126a6c25d1ed193dfaa7f4a2c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">VPHY core registers: General registers.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Address mapping for the Video PHY core. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">VPHY core registers: Dynamic reconfiguration port (DRP) registers.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">VPHY core registers: Transmitter function registers.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">VPHY core registers: Receiver function registers.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">VPHY core registers: Interrupt registers.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">User clocking registers: MMCM and BUFGGT registers.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Clock detector (HDMI) registers.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Data recovery unit registers (HDMI).</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">VPHY core masks, shifts, and register values.</div></td></tr>
<tr class="memitem:a74113375bc89436a53bce047a320afae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xvphy__hw_8h.html#a74113375bc89436a53bce047a320afae">XVPHY_VERSION_INTER_REV_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="separator:a74113375bc89436a53bce047a320afae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac5dfad9c937d8e2f86b98a5a931900df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xvphy__hw_8h.html#ac5dfad9c937d8e2f86b98a5a931900df">XVPHY_VERSION_CORE_PATCH_MASK</a>&#160;&#160;&#160;0x00000F00</td></tr>
<tr class="separator:ac5dfad9c937d8e2f86b98a5a931900df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7d6b1ef912a814220affa8290d8cf770"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xvphy__hw_8h.html#a7d6b1ef912a814220affa8290d8cf770">XVPHY_VERSION_CORE_PATCH_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="separator:a7d6b1ef912a814220affa8290d8cf770"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7c710fe411d729dcc7cfba79d5e3e710"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xvphy__hw_8h.html#a7c710fe411d729dcc7cfba79d5e3e710">XVPHY_VERSION_CORE_VER_REV_MASK</a>&#160;&#160;&#160;0x0000F000</td></tr>
<tr class="separator:a7c710fe411d729dcc7cfba79d5e3e710"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab2bc0b3efefdecdaddb10f29be2d7975"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xvphy__hw_8h.html#ab2bc0b3efefdecdaddb10f29be2d7975">XVPHY_VERSION_CORE_VER_REV_SHIFT</a>&#160;&#160;&#160;12</td></tr>
<tr class="separator:ab2bc0b3efefdecdaddb10f29be2d7975"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acc4aa2972a26e662a427e19b07311b3e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xvphy__hw_8h.html#acc4aa2972a26e662a427e19b07311b3e">XVPHY_VERSION_CORE_VER_MNR_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="separator:acc4aa2972a26e662a427e19b07311b3e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adc00e71a2ac79d5ec79419ddeae4a6af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xvphy__hw_8h.html#adc00e71a2ac79d5ec79419ddeae4a6af">XVPHY_VERSION_CORE_VER_MNR_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="separator:adc00e71a2ac79d5ec79419ddeae4a6af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae435c1eaf4380b226c5cd4cc76eb1736"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xvphy__hw_8h.html#ae435c1eaf4380b226c5cd4cc76eb1736">XVPHY_VERSION_CORE_VER_MJR_MASK</a>&#160;&#160;&#160;0xFF000000</td></tr>
<tr class="separator:ae435c1eaf4380b226c5cd4cc76eb1736"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a733b97f887f1043a8c65a74717b0d7ea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xvphy__hw_8h.html#a733b97f887f1043a8c65a74717b0d7ea">XVPHY_VERSION_CORE_VER_MJR_SHIFT</a>&#160;&#160;&#160;24</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Register access macro definitions.</div></td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a4efa6fb68e702bd91a3fb099d7ba0188"></a>
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          <td class="memname">#define XVphy_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;XVphy_In32((BaseAddress) + (RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This is a low-level function that reads from the specified register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be read from.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the specified register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xvphy__hw_8h.html#a4efa6fb68e702bd91a3fb099d7ba0188" title="This is a low-level function that reads from the specified register. ">XVphy_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="xvphy_8h.html#ae544dc0c99277e35af7ed7301741b2f0">XVphy_BufgGtReset()</a>, <a class="el" href="xvphy__hdmi_8h.html#a5c1a11ae34d28eb62747ac3e208c24ab">XVphy_ClkDetCheckFreqZero()</a>, <a class="el" href="xvphy__hdmi_8h.html#a92a46534a86b99ee8952f265ffef6adf">XVphy_ClkDetEnable()</a>, <a class="el" href="xvphy__hdmi_8c.html#acf7ae04f5605eac1c87ffef842b619f7">XVphy_ClkDetFreqReset()</a>, <a class="el" href="xvphy__hdmi_8c.html#ab0467bf2748fc0bed3b343a469ace134">XVphy_ClkDetGetRefClkFreqHz()</a>, <a class="el" href="xvphy__hdmi_8h.html#a30848af87342051f772a8080f904337a">XVphy_ClkDetSetFreqLockThreshold()</a>, <a class="el" href="xvphy__hdmi_8h.html#a58356dc6e862e4015623e9b67b7fb9ab">XVphy_ClkDetTimerClear()</a>, <a class="el" href="xvphy_8h.html#ab5c0be51d9acd79559d092d16e7d1fe8">XVphy_Clkout1OBufTdsEnable()</a>, <a class="el" href="xvphy__hdmi_8h.html#ac049d6360551ee356c21f7f8e3c583ac">XVphy_DruEnable()</a>, <a class="el" href="xvphy__hdmi_8c.html#a1560403a2fbe4ad437d011c276e25880">XVphy_DruGetRefClkFreqHz()</a>, <a class="el" href="xvphy__hdmi_8h.html#aa6cd483fd9c888c3e5b9f716ccd311c7">XVphy_DruGetVersion()</a>, <a class="el" href="xvphy__hdmi_8h.html#a6d7adb703bf8d7039bb490890267100f">XVphy_DruReset()</a>, <a class="el" href="xvphy_8h.html#af5215e0e59c2dd0f2ee47b176cd9e47e">XVphy_GetPllRefClkSel()</a>, <a class="el" href="xvphy_8h.html#a8e1cf75cf2ecce4902aeb0faca3d0c7c">XVphy_GetSysClkDataSel()</a>, <a class="el" href="xvphy_8h.html#afa18f0da25042d12e577a5e16d950476">XVphy_GetSysClkOutSel()</a>, <a class="el" href="xvphy_8h.html#aa4cef4dea102e0cbb7671d8113f9d52e">XVphy_GetVersion()</a>, <a class="el" href="xvphy_8h.html#ae11d25f939879208256c3e8155f9873c">XVphy_GtUserRdyEnable()</a>, <a class="el" href="xvphy__hdmi_8c.html#ac33c4acc75ec57ab3d51e0f1391f1baf">XVphy_HdmiDebugInfo()</a>, <a class="el" href="xvphy__hdmi_8h.html#a1f5275570d3771fb5ac18cbf2fbf642a">XVphy_HdmiGtDruModeEnable()</a>, <a class="el" href="xvphy_8h.html#ac5754f49fa0df65d75a6d62f4885b94c">XVphy_IBufDsEnable()</a>, <a class="el" href="xvphy__intr_8c.html#a75e14bbc2dcc8eeeaaed26371ae1b34c">XVphy_InterruptHandler()</a>, <a class="el" href="xvphy__intr_8c.html#a854725cac309c3302a25dbc29927c9f8">XVphy_IntrDisable()</a>, <a class="el" href="xvphy__intr_8c.html#ab0c6c186dbb5142d23a6a3b76148c37b">XVphy_IntrEnable()</a>, <a class="el" href="xvphy_8h.html#aef25e82d5f217655c1c3c3039c9e1dc3">XVphy_IsPllLocked()</a>, <a class="el" href="xvphy_8h.html#a096dbcd95256264a53fe8af27c8387fb">XVphy_MmcmLockedMaskEnable()</a>, <a class="el" href="xvphy_8h.html#a59516866f229178eca67ede70680a751">XVphy_MmcmPowerDown()</a>, <a class="el" href="xvphy_8h.html#adc182ff22a7ec230dc163f90ec5263a3">XVphy_MmcmReset()</a>, <a class="el" href="xvphy_8h.html#a1b82d1b302268e36126450121d948505">XVphy_PowerDownGtPll()</a>, <a class="el" href="xvphy_8h.html#ad1c3340164a0759e485ba914ef282dc3">XVphy_ResetGtPll()</a>, <a class="el" href="xvphy_8h.html#a3d258176c8a2cc605cdaf8f28a72559d">XVphy_ResetGtTxRx()</a>, <a class="el" href="xvphy__selftest_8c.html#a772c4c6e8f106de408926972cb2443f2">XVphy_SelfTest()</a>, <a class="el" href="xvphy_8h.html#a03e3adda3a9a41ade009735ab5849b8f">XVphy_Set8b10b()</a>, <a class="el" href="xvphy_8h.html#a15c1341136ca5bde85ab447ba9e09c56">XVphy_SetBufgGtDiv()</a>, <a class="el" href="xvphy_8h.html#ab4dbca672563dce677d06d7bbbbe23d9">XVphy_SetRxLpm()</a>, <a class="el" href="xvphy_8h.html#a4071a10340c3cda8cfb3aa3bfb4483e9">XVphy_SetTxPreEmphasis()</a>, <a class="el" href="xvphy_8h.html#a7526bb0de496313d804798dcc1df8cc8">XVphy_SetTxVoltageSwing()</a>, <a class="el" href="xvphy__hdmi_8h.html#aeaff661706441c4ab53c0e3b14b3bc52">XVphy_TxAlignReset()</a>, <a class="el" href="xvphy__hdmi_8h.html#a17fb7c16e6806cc2b654d358c5ade050">XVphy_TxAlignStart()</a>, <a class="el" href="xvphy_8h.html#a666425d750b27f1be0faeb363eb9698c">XVphy_WaitForPmaResetDone()</a>, and <a class="el" href="xvphy_8h.html#ac1c0e3c56e0d77d5d222b86be8a30cb6">XVphy_WaitForResetDone()</a>.</p>

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<a class="anchor" id="ac5dfad9c937d8e2f86b98a5a931900df"></a>
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          <td class="memname">#define XVPHY_VERSION_CORE_PATCH_MASK&#160;&#160;&#160;0x00000F00</td>
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<p>Core patch details. </p>

</div>
</div>
<a class="anchor" id="a7d6b1ef912a814220affa8290d8cf770"></a>
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          <td class="memname">#define XVPHY_VERSION_CORE_PATCH_SHIFT&#160;&#160;&#160;8</td>
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      </table>
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<p>Shift bits for core patch details. </p>

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<a class="anchor" id="ae435c1eaf4380b226c5cd4cc76eb1736"></a>
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          <td class="memname">#define XVPHY_VERSION_CORE_VER_MJR_MASK&#160;&#160;&#160;0xFF000000</td>
        </tr>
      </table>
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<p>Core major version. </p>

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<a class="anchor" id="a733b97f887f1043a8c65a74717b0d7ea"></a>
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          <td class="memname">#define XVPHY_VERSION_CORE_VER_MJR_SHIFT&#160;&#160;&#160;24</td>
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      </table>
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<p>Shift bits for core major version. </p>

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<a class="anchor" id="acc4aa2972a26e662a427e19b07311b3e"></a>
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          <td class="memname">#define XVPHY_VERSION_CORE_VER_MNR_MASK&#160;&#160;&#160;0x00FF0000</td>
        </tr>
      </table>
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<p>Core minor version. </p>

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<a class="anchor" id="adc00e71a2ac79d5ec79419ddeae4a6af"></a>
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          <td class="memname">#define XVPHY_VERSION_CORE_VER_MNR_SHIFT&#160;&#160;&#160;16</td>
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<p>Shift bits for core minor version. </p>

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<a class="anchor" id="a7c710fe411d729dcc7cfba79d5e3e710"></a>
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          <td class="memname">#define XVPHY_VERSION_CORE_VER_REV_MASK&#160;&#160;&#160;0x0000F000</td>
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<p>Core version revision. </p>

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          <td class="memname">#define XVPHY_VERSION_CORE_VER_REV_SHIFT&#160;&#160;&#160;12</td>
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<p>Shift bits for core version revision. </p>

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          <td class="memname">#define XVPHY_VERSION_INTER_REV_MASK&#160;&#160;&#160;0x000000FF</td>
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<p>Internal revision. </p>

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          <td class="memname">#define XVphy_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;XVphy_Out32((BaseAddress) + (RegOffset), (Data))</td>
        </tr>
      </table>
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<p>This is a low-level function that writes to the specified register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to write to. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit data to write to the specified register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xvphy__hw_8h.html#a03d7c5c126a6c25d1ed193dfaa7f4a2c" title="This is a low-level function that writes to the specified register. ">XVphy_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="xvphy_8h.html#ae544dc0c99277e35af7ed7301741b2f0">XVphy_BufgGtReset()</a>, <a class="el" href="xvphy__hdmi_8h.html#a92a46534a86b99ee8952f265ffef6adf">XVphy_ClkDetEnable()</a>, <a class="el" href="xvphy__hdmi_8c.html#acf7ae04f5605eac1c87ffef842b619f7">XVphy_ClkDetFreqReset()</a>, <a class="el" href="xvphy__hdmi_8h.html#a30848af87342051f772a8080f904337a">XVphy_ClkDetSetFreqLockThreshold()</a>, <a class="el" href="xvphy__hdmi_8h.html#a6e295c2b7225212e9f36ce42a6abe468">XVphy_ClkDetSetFreqTimeout()</a>, <a class="el" href="xvphy__hdmi_8h.html#a58356dc6e862e4015623e9b67b7fb9ab">XVphy_ClkDetTimerClear()</a>, <a class="el" href="xvphy__hdmi_8h.html#af08e07cf3f25577c6bab5302453897f3">XVphy_ClkDetTimerLoad()</a>, <a class="el" href="xvphy_8h.html#ab5c0be51d9acd79559d092d16e7d1fe8">XVphy_Clkout1OBufTdsEnable()</a>, <a class="el" href="xvphy__hdmi_8h.html#ac049d6360551ee356c21f7f8e3c583ac">XVphy_DruEnable()</a>, <a class="el" href="xvphy__hdmi_8h.html#a6d7adb703bf8d7039bb490890267100f">XVphy_DruReset()</a>, <a class="el" href="xvphy__hdmi_8h.html#aa09d59f3ae8499186a0e262a613cd141">XVphy_DruSetCenterFreqHz()</a>, <a class="el" href="xvphy__hdmi_8h.html#ac7aa7ca227f880fe0f77c4cbfe3d4cb9">XVphy_DruSetGain()</a>, <a class="el" href="xvphy_8h.html#ae11d25f939879208256c3e8155f9873c">XVphy_GtUserRdyEnable()</a>, <a class="el" href="xvphy__hdmi_8h.html#a1f5275570d3771fb5ac18cbf2fbf642a">XVphy_HdmiGtDruModeEnable()</a>, <a class="el" href="xvphy__hdmi_8c.html#acd09bca6664c614b29cf051367729ea3">XVphy_HdmiInitialize()</a>, <a class="el" href="xvphy_8h.html#ac5754f49fa0df65d75a6d62f4885b94c">XVphy_IBufDsEnable()</a>, <a class="el" href="xvphy__intr_8c.html#a854725cac309c3302a25dbc29927c9f8">XVphy_IntrDisable()</a>, <a class="el" href="xvphy__intr_8c.html#ab0c6c186dbb5142d23a6a3b76148c37b">XVphy_IntrEnable()</a>, <a class="el" href="xvphy_8h.html#a096dbcd95256264a53fe8af27c8387fb">XVphy_MmcmLockedMaskEnable()</a>, <a class="el" href="xvphy_8h.html#a59516866f229178eca67ede70680a751">XVphy_MmcmPowerDown()</a>, <a class="el" href="xvphy_8h.html#adc182ff22a7ec230dc163f90ec5263a3">XVphy_MmcmReset()</a>, <a class="el" href="xvphy_8h.html#a1b82d1b302268e36126450121d948505">XVphy_PowerDownGtPll()</a>, <a class="el" href="xvphy_8h.html#ad1c3340164a0759e485ba914ef282dc3">XVphy_ResetGtPll()</a>, <a class="el" href="xvphy_8h.html#a3d258176c8a2cc605cdaf8f28a72559d">XVphy_ResetGtTxRx()</a>, <a class="el" href="xvphy_8h.html#a03e3adda3a9a41ade009735ab5849b8f">XVphy_Set8b10b()</a>, <a class="el" href="xvphy_8h.html#a15c1341136ca5bde85ab447ba9e09c56">XVphy_SetBufgGtDiv()</a>, <a class="el" href="xvphy_8h.html#ab4dbca672563dce677d06d7bbbbe23d9">XVphy_SetRxLpm()</a>, <a class="el" href="xvphy_8h.html#a4071a10340c3cda8cfb3aa3bfb4483e9">XVphy_SetTxPreEmphasis()</a>, <a class="el" href="xvphy_8h.html#a7526bb0de496313d804798dcc1df8cc8">XVphy_SetTxVoltageSwing()</a>, <a class="el" href="xvphy__hdmi_8h.html#aeaff661706441c4ab53c0e3b14b3bc52">XVphy_TxAlignReset()</a>, <a class="el" href="xvphy__hdmi_8h.html#a17fb7c16e6806cc2b654d358c5ade050">XVphy_TxAlignStart()</a>, and <a class="el" href="xvphy_8h.html#a5041cead7e1fe927d645c4e681e95837">XVphy_WriteCfgRefClkSelReg()</a>.</p>

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